Recent years have witnessed a demand for a compact display drive circuit for driving a liquid crystal panel, in order to reduce a frame width of a liquid crystal display device. The size of a display drive circuit has a significant influence on the number of elements of a transistor constituting the circuit. It is therefore important to reduce the number of transistors.
(a) of FIG. 20 is a circuit diagram illustrating an arrangement of a flip-flop used as various display drive circuits of a conventional liquid crystal display device. A flip-flop 100a illustrated in (a) of FIG. 20 includes (i) a P channel transistor p22 and an N channel transistor n21 which constitute a CMOS circuit, (ii) a P channel transistor p23 and an N channel transistor n22 which constitute another CMOS circuit, (iii) a P channel transistor p21, (iv) an SB terminal, (v) an RB terminal, (vi) an INIT terminal, (vii) a Q terminal, and (ix) a QB terminal.
A gate terminal of the transistor p22, a gate terminal of the transistor n21, a drain terminal of the transistor p23, a drain terminal of transistor n22, a drain terminal of transistor p21, and the Q terminal are connected to each other. A drain terminal of the transistor p22, a drain terminal of the transistor n21, a gate terminal of the transistor p23, a gate terminal of the transistor n22, and the QB terminal are connected to each other. The SB terminal is connected to a gate terminal of the transistor p21. The RB terminal is connected to a source terminal of the transistor p21 and a source terminal of the transistor p23. The INIT terminal is connected to a source terminal of the transistor n21. A source terminal of the transistor n22 is connected to a VSS. The transistors p22, n21, p23, and n22 constitute a latch circuit LC, and the transistor p21 serves as a set transistor ST.
(b) of FIG. 20 is a timing chart showing an operation of the flip-flop 100a (in a case where an INIT signal is inactive), and (c) of FIG. 20 is a truth table of the flip-flop 100a (in the case where the INIT signal is inactive). A Q signal of the flip-flop 100a is such that (i) it is at a low level (inactive) during a time period in which an SB signal is at a low level (active) and an RB signal is at a low level (active), (ii) it is at a high level (active) during a time period in which the SB signal is at a low level (active) and the RB signal is at a high level (inactive), (iii) it is at a low level (inactive) during a time period in which the SB signal is at a high level (inactive) and the RB signal is at a low level (active), and (iv) it is in a retention state during a time period in which the SB signal is at a high level (inactive) and the RB signal is at a high level (inactive) (see (b) and (c) of FIG. 20).
For example, during a time period t1 shown in (b) of FIG. 20, the Q terminal receives Vdd (high level) from the RB terminal. Accordingly, the transistor n21 is turned on, so that the QB terminal receives Vss (low level). Then, during a time period t2, the SB signal is turned to a high level, so that the transistor p21 is turned off. Accordingly, the state of the time period t1 is maintained. During a time period t3, the RB signal is turned to a low level. Accordingly, the Q terminal temporarily receives Vss+Vth (a threshold voltage of the transistor p23) via the transistor p23. This turns on the transistor p22, so that the QB terminal receives Vdd (high level). Further, since the QB terminal receives Vdd, the transistor n22 is turned on. Accordingly, the Q terminal receives Vss. Note that in a case where both the SB signal and the RB signal are turned to a low level (active), the Q terminal temporarily receives Vss+Vth via the transistor p21. This turns on the transistor p22, so that the QB terminal receives Vdd (high level). Further, since the QB terminal receives Vdd, the transistor n22 is turned on. Accordingly, the Q terminal receives Vss.
As described above, the flip-flop 100a has an arrangement in which (i) the transistors p22, n21, p23, and n22 (two CMOS circuits) constitute a latch circuit, (ii) the RB terminal is connected to (a) the source terminal of the transistor p21 which serves as a set transistor ST and (b) the source terminal of the transistor p23, and (iii) the source terminal of the transistor n21 is connected to the INIT terminal. With the arrangement, it is possible to carry out a setting operation, a latching operation, a resetting operation, priority determination (when the SB signal and the RB signal are turned to be active simultaneously), and initialization. As described above, when the SB signal and the RB signal of the flip-flop 100a are turned to be active simultaneously, the RB signal (reset) has priority so that the Q signal and the QB signal are turned to be inactive.
(a) of FIG. 21 is a circuit diagram illustrating an arrangement of a flip-flop 100b which is a modified example of (a) of FIG. 20. The flip-flop 100b illustrated in (a) of FIG. 21 includes (i) a P channel transistor p24 and an N channel transistor n24 which constitute a CMOS circuit, (ii) a P channel transistor p25 and an N channel transistor n25 which constitute another CMOS circuit, (iii) an N channel transistor n23, (iv) an S terminal, (v) an R terminal, (vi) an INITB terminal, (vii) a Q terminal, and (viii) a QB terminal.
A gate terminal of the transistor p24, a gate terminal of the transistor n24, a drain terminal of the transistor p25, a drain terminal of transistor n25, a drain terminal of transistor n23, and the QB terminal are connected to each other. A drain terminal of the transistor p24, a drain terminal of the transistor n24, a gate terminal of the transistor p25, a gate terminal of the transistor n25, and the Q terminal are connected to each other. The S terminal is connected to a gate terminal of the transistor n23. The R terminal is connected to a source terminal of the transistor n23 and a source terminal of the transistor n25. The INITB terminal is connected to a source terminal of the transistor p24. A source terminal of the transistor p25 is connected to a VDD. A source terminal of the transistor n24 is connected to a VSS. Here, the transistors p24, n24, p25, and n25 constitute a latch circuit LC, and the transistor n23 serves as a set transistor ST.
(b) of FIG. 21 is a timing chart showing an operation of the flip-flop 100b (in a case where an INITB signal is inactive), and (c) of FIG. 21 is a truth table of the flip-flop 100b (in the case where the INITB signal is inactive). A Q signal of the flip-flop 100a is such that (i) it is in a retention state during a time period in which an S signal is at a low level (inactive) and an R signal is at a low level (inactive), (ii) it is at a low level (inactive) during a time period in which the S signal is at a low level (inactive) and the R signal is at a high level (active), (iii) it is at a high level (active) during a time period in which the S signal is at a high level (active) and the R signal is at a low level (inactive), and (iv) it is at a low level (inactive) during a time period in which the S signal is at a high level (active) and the R signal is at a high level (active) (see (b) and (c) of FIG. 21).